With CMOS technology entering FinFET in 14 nanometers (nm), conventional lithography is no longer capable for patterning fine pitches. The self-align-dual-patterning (SADP), self-aligned quadruple patterning (SAQP), or sidewall image transfer (SIT) process enables the small pitch patterning in forming Fins, gates, or even in BEOL (Back-End-Of-The-Line) metal connections at 7 nanometers node and beyond. Spacer defined lithography (SIT) only offers one CD (critical dimension) such as widths for fine lines.